1. Field of the Invention
The present invention relates to input protection circuit devices, and more particularly, to a structure of a protection circuit unit and arrangements of a signal input unit and a power supply potential input unit.
2. Description of the Background Art
The problem of the so-called electrostatic breakdown in which internal devices are damaged when a surge current is applied to an input pad or the like or when a surge current is applied to the power supply during operation of a semiconductor device is encountered in the manufacturing process of a semiconductor device. An input protection circuit device is provided to protect the internal device from such a surge current.
An example of a conventional input protection circuit device will be described hereinafter with reference to FIG. 20.
An input protection circuit device includes a first resistor 103 and a second resistor 104 connected in series in an input signal line 109 connecting an input signal pad 106 and an internal circuit 108, and field transistors 101 and 102 connected between the portion of input signal line 109 between first and second resistors 103 and 104 and a power supply (Vcc) 105 or ground GND 107, respectively. First resistor 103 is formed of a polysilicon. Field transistor 101 has its source side connected to input signal line 109, and its drain side connected to power supply (Vcc) 105. Field transistor 102 has its drain side connected to input signal line 109 and its source side connected to GND 107. The potential of the each gate thereof is not fixed, and attains a floating state.
When a surge current higher than the potential of power supply (Vcc) 105 is applied from input pad 106 in the above-described structure, a depletion layer expands between the source and drain of field transistor 101 to provide electrical connection therebetween. When a surge current lower than the potential of GND 107 is applied, a depletion layer between the source and drain of field transistor 102 expands to provide electrical connection therebetween. Therefore, the potential of input signal line 109 between first and second resistors 103 and 104 is maintained at a level between the voltage of power supply (Vcc) 105 and the potential of GND 107. In this way, the surge current applied to input pad 106 is prevented from flowing towards internal circuit 108.
To accommodate for the trend of larger scale integration and high density in recent devices, miniaturization in the interconnection wiring connecting semiconductor circuit devices is effected. Such miniaturization of interconnection wiring induces the problem of degrading the endurance of electrostatic breakdown. Increase in the integration density is required also in an input protection circuit device corresponding to devices scaled to higher densities.
Another example of an input protection circuit device of a case in which a surge current is applied to the power supply of the semiconductor device will be described.
Referring to FIG. 21, this input protection circuit includes a diode 110 connected between power supply (Vcc) 105 and GND 107.
Such an input protection circuit relates greatly to a problem inherent in recent semiconductor devices including a CMOS transistor directed to reduce power consumption. More specifically, there is a problem of a latch up phenomenon associated with miniaturization of devices including a CMOS transistor.
FIG. 22 shows a sectional view and an equivalent circuit of a CMOS device. Referring to FIG. 22, this device includes a pMOS transistor 111 formed on an n type substrate 115, and an nMOS transistor 112 formed on a P well 116 of n type substrate 115. Power supply (Vcc) 105 is connected to a p.sup.+ diffusion layer 113 of pMOS transistor 111, and an n.sup.+ diffusion layer 114 of nMOS transistor 112 is connected to GND 107. A p-n-p structure is formed by p.sup.+ diffusion layer 113, n type substrate 115, and P well 116. An n-p-n structure is formed by n.sup.+ diffusion layer 114, P well 116 and n substrate 115. These can be regarded as a lateral type p-n-p bipolar transistor and a vertical type n-p-n bipolar transistor formed parasitically in a CMOS device. These two bipolar transistors function as a thyristor, whereby a current flows from p.sup.+ diffusion layer 113 towards n substrate 115 by a surge current applied to power supply (Vcc) 105. Difference in potential between p.sup.+ diffusion layer 113 and n type substrate 115 is generated to cause current to flow from p.sup.+ diffusion layer 113 towards P well 116. Here, difference in potential between n type substrate 115 and P well 116 is generated to cause a flow of a current of a greater level from n type substrate 115 towards n.sup.+ diffusion layer 114, Thus, the current of power supply (Vcc) 105 induces the latch up phenomenon towards GND 107.
FIG. 23 shows the flow of current 130 from power supply (Vcc) 105 towards GND 107.
Such a latch up phenomenon is occurring more frequently since the distance between p.sup.+ diffusion layer 113 and P well 116 and also the distance between n.sup.+ diffusion layer 114 and n type substrate 115 are reduced as the CMOS device is increased in integration density. This means that even a surge current of a low level will trigger the generation of a latch up phenomenon.
A further example of an input protection circuit device applied in the power supply of a static random access memory (referred to as SRAM hereinafter) will be described hereinafter.
FIG. 24 is a block diagram showing a structure of a general SRAM. Referring to FIG. 24, an SRAM 126 includes a memory cell array 117 for storing a data signal of stored information, a row address buffer 118 and a column address buffer 119 for receiving an external address signal to select a memory cell forming a unitary storage circuit, a row decoder 120 and a column decoder 121 for specifying a memory cell by decoding the received address signal, a sense amplifier 122 for amplifying and reading out the signal stored in the specified memory cell, a data input/output buffer 123 for data input/output, a R/W control circuit 124 for controlling reading/writing, and a write driver 125 for writing information. SRAM 126 operates by power supply (Vcc) 105.
In order to prevent any erroneous operation due to noise, some recent SRAMs have a power supply for the data input output circuit in data output buffer 123 provided independent of the power supply for the other input circuits. More specifically, the SRAM includes two types of power supplies for the output circuit (Vccq) and for the internal circuit (Vcc).
FIG. 25 is a sectional view and an equivalent circuit diagram of a CMOS transistor used as an output transistor in an output circuit of such an SRAM. Referring to FIG. 25, the structure of the output circuit of the SRAM is basically similar to that of FIG. 22, provided that a second power supply (Vccq) 127 is connected to p.sup.+ diffusion layer 113 of pMOS transistor 111, and first power supply (Vcc) 105 is connected to n type substrate 115 via an n.sup.+ diffusion layer 128 formed in n type substrate 115. The set voltage has a relationship of first power supply (Vcc) &gt;second power supply (Vccq). For example, Vcc=3.3 V and Vccq=2.5 V are set.
In powering on the external power supply of the SRAM and turning on the first power supply (Vcc) and the second power supply (Vccq) in the above-described structure, there is a possibility that the second power supply (Vccq) becomes higher than the first power supply (Vcc) in transition. In this case, the output transistor may induce a latch up phenomenon, similar to that described with reference to FIGS. 22 and 23. More specifically, referring to FIG. 25, a current flows from p.sup.+ diffusion layer 113 of pMOS transistor 111 to which second power supply (Vccq) 127 is connected towards n type substrate 115 or n.sup.+ diffusion layer 128. Therefore, a potential difference between p.sup.+ diffusion layer 113 and n type substrate 115 is generated to cause a current to flow from p.sup.+ diffusion layer 113 towards P well 116. Also, the potential difference between n type substrate 115 and P well 116 is generated to cause a flow of a greater current from n type substrate 115 to n.sup.+ diffusion layer 114.
Thus, there is a problem that the current flowing from p.sup.+ diffusion layer 113 towards P well 116 due to the potential of the second power supply (Vccq) becoming higher than that of the first power supply (Vcc) will trigger a latch up phenomenon of an output transistor.
Degradation in the electrostatic breakdown endurance due to miniaturization of the interconnection wiring according to increase in integration density of devices cannot be prevented in a conventional input protection circuit device. It was also not possible to sufficiently prevent the generation of a latch up phenomenon in an output transistor of a device by a surge current applied to the power supply. Furthermore, generation of a latch up phenomenon in an output transistor of a device having two different potentials of power supplies for noise measures cannot be prevented in the case where the relation of the set potentials of the two different power supplies is reversed.